The present invention relates to a semiconductor integrated logic circuit and, more particularly, to a programmable logic array whose structural elements can be easily tested for correct operation.
As a result of the marked increase in the integration density in semiconductor circuit devices, which has made it possible to form a vast number of circuit elements in a single semiconductor chip, there has been an increasing demand for greater versatility and function varieties for circuits formed in such semiconductor chips as well as for the adaptability to mass production. One of the integrated circuits developed to meet these requirements is a programmable logic array (PLA) which is comprised of a logical product (AND) term generator and a logical sum (OR) term generator. The AND term generator is an AND array including a plurality of AND elements arrayed in a matrix, while the OR term generator is an OR array including a plurality of OR elements arrayed in a matrix so connected to the AND array as to take an OR operation of a given combination of the output signals from the AND array.
Such a PLA is disclosed, for example, in the U.S. Pat. Nos. 3,566,153 and 3,702,985. The above-mentioned PLA is programmable so that any user may assemble a desired random logic by the use of a single fabrication mask, giving high flexibility in use and attaining excellent mass production allowing the mask patterns to be standardized. However, such a PLA has the disadvantage in that a greater amount of test data for testing the structural elements used is needed with the improvement of the integration density. More particularly, when any one of the AND elements of the PLA is defective, the output signal of the AND gate is "0". For this reason, the defective element is readily detected. On the other hand, when any one of the OR elements is defective, the output signal of the OR array as a whole is "1". As a result, the detection of the defective OR element becomes difficult, requiring a great amount of test data and test time.